Next Generation LVDS-LVPECL Clock Reference

  • March 28, 2012

Dynamic Engineers is pleased to announce the release of a new generation of  LVDS / LVPECL clock oscillator reference sources with integrated phase jitter that is 10 times lower than other high performance options in the market.

Customers using the new XO7500VLP platform will benefit from phase jitter levels below 100 femto-seconds integrated from 12KHz to 20MHz offset.    Operating from a 3.3V supply, the XO7500VLP offers a crystal oscillator based on the latest very low phase noise IC chip architectures, and highly  advanced quartz crystal design and processing techniques.  This combination of technologies  makes this XO highly suitable for next generation broadband access communication networks, and digital signal processing applications requiring maximum dynamic range and minimum bit error rates.

With QA testing and light assembly operations in both Asia and the US,  DEI can offer customers a more comprehensive performance test profile and deeper understanding of standard products where applications demand it.  We have over twenty years of production engineering knowledge of low phase jitter XO behavior and best in class processing techniques to achieve high levels of long term reliability in the customer specific applications.

Additional features of the new XO7500VLP solution include the following  customer select options:

This device offers a discrete output frequency within an operating range of 32 MHz to 200 MHz with LVPECL complimentary outputs.  For LVDS complimentary outputs, the operating frequency range is 106.25 MHz to 200 MHz.  An optional ENABLE / DISABLE function is available on PAD 1 or 2.

A selection of overall frequency stability choices are available dependent upon operating temperature range and output frequency.  The XO is packaged in a 5.0 x 7.0 x 1.8 mm SMD profile package.

For other custom requirements please consult with DEI Sales and Application Engineering.

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